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Yusuf Leblebici

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Yusuf Leblebici

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Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

A Simulation Methodology for Reliability Analysis in Multi-Core SoCs

Analysis and Optimization of MPSoC Reliability

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Part I - Circuit Design

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

Design for Reliability of Nanometer-Scale Electronics under High Defect Density

Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design-Flow and Implementation

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Low-Power Adaptive Bias/Clock Generator Using 0.18um CMOS Technology for Multi-Core Continuous Voltage and Frequency Scaling