Design for Reliability of Nanometer-Scale Electronics under High Defect Density

High defect density exhibited by nanoelectronic technologies, and parameter variability already affecting the operation of very-deep submicron CMOS systems demand for a combination of specific solutions, focusing at each various levels of abstraction in the development design-flow. Where traditionally applied methods fail under massive defect densities, we propose a top-down development strategy where the hardware overhead is adapted to the desired level of reliability. A CAD software tool supporting the methodology has been developed (Fig. 1(a)), with the intension to make the reliability enhancement process transparent to the designer, who is only expected to provide high-level specifications, and technology-related information as issued by foundries. The impact of sixteen mostly encountered circuit failures are evaluated using Monte Carlo SPICE simulations, and based on a replacement transistor macro-model. A fault-absorbing four-layer architecture composed of an input layer, a second layer with very limited redundant digital units (as few as one redundant unit), an analog averaging unit as third layer, and a thresholding decision unit form the architectural abstraction level [1]. After selection of the appropriate redundancy factor, the software tool partitions the initial netlist, and inserts redundant units and output layers three and four, according to a selected granularity level, which has been observed to be optimally chosen in the order of eight gate-equivalents [2]. Circuits have been developed in 180 and 90nm technologies, thus implementing all four layers at circuit abstraction level. Software simulations have been carried out validating the method on small-size circuits, in the range of Boolean gates, or a full-adder, and using single-ended and differential design styles. Monte Carlo simulations are conveniently replacing exhaustive simulation and help limit the computational burden. Comparative results are shown on Fig. 1(b), where the advantage of differential cascode switch logic (DCVS) over single-ended CMOS is evidenced. A large-scale AES crypto-chip based on the proposed method is currently in fabrication; the proposed method and software tool have been applied in the development of robust standard cells.