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Wladyslaw Grabinski

Related publications (16)

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The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. T ...

IEEE2019

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The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and ...

IEEE2018

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The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS techno ...

Ieee2015

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In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices ...

American Institute of Physics2014

Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 x 10(19) cm(-3) n-type channel doping, 5-20 nm Si nanowire wi ...

Pergamon-Elsevier Science Ltd2014

Compact Modeling of Homojunction Tunnel FETs

Mihai Adrian Ionescu, Wladyslaw Grabinski, Antonios Bazigos, Luca De Michielis, Cem Alper, Arnab Biswas, Nilay Dagtekin

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supp ...

IEEE2014

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

IEEE2013

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

Mihai Adrian Ionescu, Wladyslaw Grabinski, Arnab Biswas, Surya Shankar Dan

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured ...

Elsevier2012

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

Mihai Adrian Ionescu, Wladyslaw Grabinski, Arnab Biswas, Surya Shankar Dan

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET ...

Institute of Electrical and Electronics Engineers2012

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In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

Elsevier2012