Person

Panagiotis Athanasopoulos

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Related publications (8)

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The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

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An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

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A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

2012

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This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

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This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

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Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the c ...

2009

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The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008