Publications by Vasileios Pavlidis

An Enhanced Design Methodology for Resonant Clock Trees

Giovanni De Micheli, Xifan Tang, Vasileios Pavlidis, Somayyeh Rahimian Omam

Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, sig ...

American Scientific Publishers2013

3.5-D Integration: A Case Study

Giovanni De Micheli, Vasileios Pavlidis, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Ciprian Seiculescu

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

2013

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Giovanni De Micheli, Xifan Tang, Vasileios Pavlidis, Hu Xu, Wayne Burleson

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Institute of Electrical and Electronics Engineers2013

Effects of Process Variations on 3-D Global Clock Distribution Networks

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Assoc Computing Machinery2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional ...

2012

Low-power clock distribution networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional cl ...

2012

A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric

Vasileios Pavlidis

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the pr ...

2012

Inter-Plane Communication Methods for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Three-dimensional (3-D) integration is an emerging candidate for implementing high performance multifunctional systems-on-chip. Employing an efficient medium for data communication among different planes is a key factor in achieving a high performance 3-D ...

American Scientific Publishers2012

Enhanced Wafer Matching Heuristics for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Ieee2012

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu, Wayne Burleson

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Ieee2012