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Mikhail Asiatici

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Mikhail Asiatici

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires

Virtualized Execution Runtime for FPGA Accelerators in the Cloud