Silicon Nanowires Patterning by Sidewall and Nano-Oxidation Processing
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Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always be ...
Non volatile flash memories based on nanoparticles are one of the possible routes to further downscaling of CMOS technology. The increase of scale integration should involve some new features for memory cells such as Coulomb blockade and quantized charging ...
Stencil lithography is an innovative method for patterning that has a great flexibility from many points of view. It is based on shadow mask evaporation using thin silicon nitride membranes that allow the patterning of sub-100 nm features up to 100 μm in a ...
Photoluminescence (PL) spectroscopy has been demonstrated as a suitable technique to characterize Si nanocrystal-based non-volatile memory devices (Carrada et al. APL 2005). These are formed by a single plane of Si nanocrystals (NCs) buried in the gate oxi ...
The necessity of applying fault-tolerant techniques to increase the reliability of future nano-electronic systems is an undisputed fact, dictated by the high density of faults that will plague these chips. The averaging and thresholding fault-tolerant tech ...