Publications related to Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Xifan Tang, Gain Kim

Nowadays, Field Programmable Gate Arrays (FPGA) exploit Look-Up Tables (LUTs) to generate logic functions. A K-input LUT can implement any Boolean functions with K inputs. Thanks to this flexibility, LUTs remained concep ...

2015

Faster ECC over $\mathbb{F}_{2^{521}-1}$

Robert Granger

In this paper we present a new multiplication algorithm for residues modulo the Mersenne prime

2^{521}−1

. Using this approach, on an Intel Haswell Core i7-4770, constant-time variable-base scalar multiplication on NIST’s (and SECG’s) curve P-521 requires ...

Springer Berlin Heidelberg2015

Improved carry chain mapping for the VTR flow

Paolo Ienne, Grace Zgheib, David Novo Bruna, Ana Petkovska

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

IEEE2015

A New Basic Logic Structure for Data-Path Computation

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Nowadays, Field Programmable Gate Arrays (FPGA) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these app ...

2014

Non-LUT field-programmable gate arrays

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Generalised Mersenne Numbers Revisited

Robert Granger

Generalised Mersenne Numbers (GMNs) were defined by Solinas in 1999 and feature in the NIST (FIPS 186-2) and SECG standards for use in elliptic curve cryptography. Their form is such that modular reduction is extremely efficient, thus making them an attrac ...

2013

Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs, invited paper

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Silicon NanoWire (SiNW) based Field Effect Tran- sistors (FETs) are promising candidates to extend Moore’s law in the coming years. Recently, Double-Gate (DG) SiNWFETs have been demonstrated to allow on-line configurability of n -type and p -type device po ...

2013

Liftings of reduction maps for quaternion algebras

Dimitar Petkov Jetchev

We construct liftings of reduction maps from complex multiplication (CM) points to supersingular points for general quaternion algebras and use these liftings to establish a precise correspondence between CM points on indefinite quaternion algebras with a ...

Oxford University Press2013

Closing the Gap between FPGA and ASIC

Hadi Parandeh Afshar

Despite many advantages of Field-Programmable Gate Arrays (FPGAs), they fail to take over the IC design market from Application-Specific Integrated Circuits (ASICs) for high-volume and even medium-volume applications, as FPGAs come with significant cost in ...

EPFL2012

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

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Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

Faster ECC over $\mathbb{F}_{2^{521}-1}$

Improved carry chain mapping for the VTR flow

A New Basic Logic Structure for Data-Path Computation

Non-LUT field-programmable gate arrays

Generalised Mersenne Numbers Revisited

Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs, invited paper

Liftings of reduction maps for quaternion algebras

Closing the Gap between FPGA and ASIC

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

Faster ECC over $\mathbb{F}_{2^{521}-1}$

Closing the Gap between FPGA and ASIC

Improved carry chain mapping for the VTR flow

Non-LUT field-programmable gate arrays

A New Basic Logic Structure for Data-Path Computation

Generalised Mersenne Numbers Revisited

Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs, invited paper

Liftings of reduction maps for quaternion algebras