Efficiency enhancement and frequency-tunable capability in linear CMOS RF power amplifiers for wireless applications

This research work deals with the design of linear CMOS RF power amplifiers. Two important aspects are treated: efficiency enhancement and frequency-tunable capability. For this purpose, two different integrated circuits were realized in a 0.11 µm technology, each one addressing a different aspect. With respect to efficiency enhancement, a dynamic supply RF power amplifier was realized. The circuit was designed for an operating frequency of 5.2 GHz, but measurements were also performed at 2.4 GHz. The integrated circuit includes a class A amplifier and a high-efficiency, switched-mode modulator. It occupies an area of 1.35 mm2. Two-tone measurement results at 2.4 and 5.2 GHz showed that the system can deliver over 16 dBm (40 mW) linear output power with efficiencies of 22.7% and 12.6%, respectively. Compared to a constant 2.5 V supply operation, the power amplifier operating with the dynamic supply delivers higher linear output power. Moreover, a relative efficiency improvement of a factor of 2.3 at 2.4 GHz and of a factor of 1.6 at 5.2 GHz at low output power levels is achieved. OFDM measurements at 2.4 GHz demonstrated that for an EVM lower than 3% and for an equal output power of 11 dBm (12.6 mW), the absolute improvement in efficiency is over 3.2%. In this work we also propose a tunable impedance matching network for use in multiband RF power amplifiers. This novel network is based on coupled inductors. A frequency-tunable RF power amplifier using this network was designed for operation at 3.7 and 5.2 GHz. Simulation results for the complete system integrated in a CMOS technology showed good results. However, the frequency-tunable behavior could not be observed in the characterization of the integrated circuit because of the low coupling factor of the integrated coupled inductors. A hybrid implementation using the integrated CMOS power amplifier, a discrete commercial RF transformer and a discrete bipolar transistor to control the current in the secondary winding of the transformer was carried out. The circuit was designed for operation at 200 and 300 MHz. The measurements have shown that at 200 MHz a relative improvement in efficiency of a factor of 1.4 was achieved. Moreover, less distortion was generated with the proposed tunable output matching network. The hybrid implementation allowed us to demonstrate the feasibility of the frequency-tunable RF power amplifier based on coupled inductors.

Low-Noise, High-Density Microelectronics for Multi-Mode Screening of Excitable Biological Cells

Urs Alexander Müller

In the past decades, two recording tools have established themselves as the working horses in the field of electrophysiological cell research: the microelectrode array (MEA) and the optical fluorescence imaging. The former is a grid of miniature electrodes allowing to monitor and stimulate cell networks; the latter uses voltage-sensitive dyes (VSDs) rendering the membrane potential visible. So far, researchers trying to combine these two measurement methods face complex electro-optical setups that suffer from the limitations of both techniques. On this ground, it is highly desirable to have a new tool at hand that (a) implements both measurement methods in a single device, (b) offers a high spatio-temporal resolution for both the electrical and the optical sensors, (c) is compact, (d) is easy to handle, and (e) allows long-term measurements. The project, this work is part of, aims to achieve these goals by means of a new concept: the multi-mode sensor array (MMSA). It consists of two parts: (1) a quartz-based microfabricated biointerface housing the sensing devices, i.e. platinum electrodes and amorphous silicon photodiodes; (2) an application specific integrated circuit (ASIC) for the amplification and the conditioning of the detected signals. The two devices are flip-chip bonded together by high-density indium bumps. The resulting measurement tool features a sensor array containing 1024 electrodes and 3072 photodiodes at a pitch of 60 μm and 30 μm, respectively. The main objective of this work is the development of said ASIC with the main task being the design of low-noise, high-density electronic circuits to read the signals detected by the biointerface electrodes and photodiodes. Secondary goals are the packaging of the system and the development of a data acquisition platform to visualise and analyse the measured values. In the course of this dissertation, two ASIC versions were designed: the MMSA I and MMSAII chips. With regard to the electrode low-noise amplifier (LNA), the two versions exhibit substantially different architectures. The MMSAI LNA features a fully-differential architecture, two amplification stages with selectable gain iii Abstract (60/50 dB) and a stable bandwidth of 10 kHz, and two integrated offset compensation techniques. While the measured gain and bandwidth are in good agreement with the simulations, the noise is substantially higher than anticipated since flicker noise was not taken into account in the circuit analysis. Based on the experiences from the MMSA I chip, the second ASIC was developed with a single-ended architecture with a folded-cascode amplifier at its core. It exhibits a gain of 52 dB, a bandwidth of 52 kHz, an average noise of 26 μVrms, and a power consumption of less than 85 μW. The offset compensation allows to deal with input-referred offset in a total range of 40 mV. Furthermore, each pixel was equipped with a sample & hold buffer and a programmable stimulation circuitry. The former stores the amplified signal locally thereby realising an electronic shutter for the electrode signals; the latter is centered around a SRAM (static random access memory) cell and permits the creation of complex stimulation patterns on the array. Comparing the design with literature reveals the competitiveness of the circuit in terms of noise efficiency factor versus area. For the treatment of the photodiode signals, the three-transistor active pixel sensor (APS) architecture is employed due to its simplicity and compactness. To maximise the sensitivity of the sensor, very small transistor dimensions were chosen, thereby minimising the capacitance. The measured responsivity ranges from 0.75 V/μWμs to 0.91 V/μWμs depending on the wavelenght of the incident light. The detectable amplitude can be adjusted by choosing an appropriate integration time. The developed package provides for the biocompatibility of the system, a stable casing, thermal dissipation, a container for the cell culture and nutrient solution, and modularity for easy exchange. The data acquisition platform transfers data at a rate of up to 35 MB/s to a computer via USB 2.0. Furthermore, it offers the creation of protocols to define the course of experiments including the choice of stimulation signal waveform, stimulation patterns, timing information, and recording options.

EPFL2012

Methodology for the digital calibration of analog circuits and systems

Marc Pastre

This thesis presents a complete methodology for the digital calibration of analog circuits. It shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. In addition, three applications of the methodology are proposed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. An additional up/down converter is suggested for the compensation of continuoustime analog signal processing circuits. The first application shows how the sub-binary M/2+M structure can be employed as a conventional digital-to-analog converter if two calibration and radix conversion algorithms are implemented. The second application, a SOI 1T DRAM, is then presented. An automatic reference current generation for memory reading is described. A digital algorithm chooses a suitable value which compensates several circuit imperfections together, from the sense amplifier offset to the dispersion of the memory read currents. The third application is the calibration of the sensitivity of a current measurement microsystem based on a Hall magnetic field sensor. An integrated reference generates a magnetic field for calibration. Using a variant of the chopper modulation, the spinning current technique, combined with a second modulation of the reference signal, the sensitivity of the complete system is continuously measured without interrupting normal operation. Modulation and demodulation schemes allowing the joint processing of both external and reference magnetic fields are proposed. Additional circuit techniques for extracting the very low reference signal are presented. The implementation of the microsystem is then discussed. The realization of the blocks composing the system is detailed, and circuit issues are presented. Finally, measurements validate the calibration principle. A thermal drift lower than 50 ppm/°C is achieved. This is 6 to 10 times less than in state-ofthe-art implementations. Furthermore, the calibration technique also compensates drifts due to mechanical stresses and ageing.

EPFL2005

Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift diffusion. In this case the conductivity of the substrate is spatially modulated and this effect is particularly important in high injection regime. In this work a description of the coupling between majority and minority drift diffusion currents is presented. A distributed model of the substrate is then proposed to take into account the conductivity modulation and its feedback on diffusion processes. The model is expressed in terms of equivalent circuits in order to be fully compatible with circuit simulators. The simulation results are then discussed for diodes and bipolar transistors and compared to the ones obtained from physical device simulations and measurements. (C) 2014 Published by Elsevier Ltd.