Energy efficiency enhancement of sub-threshold digital CMOS
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With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integra ...
The aim of this research is to develop and to evaluate devices and circuits performances based on ultrathin nanograin polysilicon wire (polySiNW) dedicated to room temperature operated hybrid CMOS-"nano" integrated circuits. The proposed polySiNW device is ...
The quickening pace of the MOSFET technology scaling has pushed the MOSFET dimension towards 10 nanometer channel length, where it is going to face the following fundamental and performance limiting factors: (i) electrostatic limits, (ii) source to drain t ...
Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...
This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...
Standard static CMOS logic is responding to the requirement of high frequency and low power of digital systems. However, the digital switching noise generated by this logic is not suited for the design of performance mixed-signal integrated systems. In mix ...
This paper presents a detailed analysis of CSL (Current Steering Logic) [1] and compares its characteristics with FSCL (Folded Source Coupled Logic) [1,2,3], two logic families intended to be applied in mixed-mode CMOS circuits. These logic families genera ...
Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degrada ...
Tuning and high frequency capabilities and dynamic range performance of continuous-time oscillators and filters, using the weak inversion operation mode of a low-cost conventional 0.5 μm CMOS technology and multi-tanh linearisation technique are examined. ...
This paper presents a detailed analysis of the CMOS Current Steering Logic (CSL) technique and compares experimentally its digital switching noise to that of the CMOS static logic. Theoretical analysis of the CSL inverter is developed. More complex gates u ...