Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
In this paper, we have used the partially depleted SOI MOSFET to measure the intensity of light. The charge pumping technique was used to get rid of the photogenerated carriers in the body in an attempt to keep the drain current constant. Using this techni ...
The influences of trapped charges on carrier transport in carbon nanotubes (CNTs) are studied using CNT field-effect transistors with a partial top-gate and a global back-gate. Trapped charges induced by the global back-gate voltage sweeping (+/- 20 V) pro ...
The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall pr ...
Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always be ...
A new architecture of a Hall microsystem for low-power applications is presented. The innovation in this paper lies in the re-use of the electric current for biasing of several parts in the microsystem permitting substantial reduction of the current consum ...
we report a new single photon avalanche diode (SPAD) implemented in a commercially available high-voltage CMOS technology. The SPAD was designed with relatively low-doped layers to form p-/n- junction, instead of commonly adopted p+/n- or n+/p- structures. ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007
We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from beta-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of abo ...
Organic FET transistors (OFETs) were fabricated on silicon substrates using pentacene as active organic layer and gold source and drain contacts. OFETs were used as test structures in order to study carriers photogeneration effect in organic layers. Photog ...
The perovskite SrHfO3 can be a potential candidate among the high-permittivity materials for gate oxide replacement in future metal-oxide semiconductor field-effect transistor technology. Thin films of SrHfO3 were grown by molecular beam epitaxy and compar ...
This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, ...