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A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

Related publications (38)

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We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...

Institute of Electrical and Electronics Engineers2011

A 16-channel 220 µW neural recording IC with embedded delta compression

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...

2011

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In many of today’s system-on-chip (SoC) designs, the cores are partitioned into multiple voltage and frequency islands (VFIs), and the global interconnect is implemented using a packetswitched network on chip (NoC). In such VFI-based designs, the benefits ...

Institute of Electrical and Electronics Engineers2010

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To mat ...

2010

An Integrated CMOS Receiver Chip for NMR-Applications

Giovanni Boero, Jens Anders, Paul Sangiorgio

We present the first CMOS-only receiver chip for NMR-applications at 300 MHz. The system consists of an on-chip reception coil, a tuning-capacitor, a downconversion-mixer and a low-frequency gain-stage as well as biasing and offset-compensation circuitry. ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V pow ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Cutting-edge CMOS neurochips, which consist of a Microelectrode Array (MEA) manufactured on top of CMOS circuitry, allow the recording of the electrical activity of neural networks in-vitro, and their stimulation. As CMOS technology continues to scale down ...

2008

An ultra low power 8-bit current-mode successive approximation (SAR) analog-to-digital (ADC) converter for Wireless Sensor Network (WSN) applications is presented. The proposed ADC contains a new asynchronous clock generator, which works only during data p ...

2007

The paper presents the programmable multiphase clock generator for switched-capacitor finite impulse response (SC FIR) circular memory filters. The proposed programmable clock circuit enables easy division of such kind of filters into different orders smal ...

2006

The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...

EPFL2006