Publications related to Flexible Ultra Low Power Successive Approximation Analog-to-Digital Converter with Asynchronous Clock Generator

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

Minimally invasive monitoring of the electrical activity of specific cortical areas using implantable microsystems offers the promise of diagnosing neurological diseases, as well as detecting and identifying neural activity patterns which are specific to a ...

EPFL2012

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

David Atienza Alonso, Pierre Vandergheynst, Nadia Khaled, Hossein Mamaghanian

The long-standing analog-to-digital conversion paradigm based on Shannon/Nyquist sampling has been challenged lately, mostly in situations such as radar and communication signal processing where signal bandwidth is so large that sampling architectures cons ...

2012

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring

David Atienza Alonso, Giovanni Ansaloni

The objective of the IcyHeart project is to investigate and demonstrate a highly integrated and power-efficient microelectronic solution for remote monitoring of a subject’s electrocardiogram (ECG) signals. A complete System-on-a-Chip (SoC) is being develo ...

IEEE Press2012

A 16-channel 220 µW neural recording IC with embedded delta compression

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...

2011

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

Rafal Tomasz Dlugosz

We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...

Institute of Electrical and Electronics Engineers2011

Clock Distribution Networks in 3-D Integrated Systems

Vasileios Pavlidis

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock di ...

2011

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Seyed Armin Tajalli, Yusuf Leblebici

A current-mode

\Delta\Sigma

analog-to-digital data converter (ADC) for biomedical readout front-end systems is being presented. The core of this circuit is a current-controlled ring oscillator (CCO) whose oscillation frequency is proportional to the inpu ...

2010

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

In many of today’s system-on-chip (SoC) designs, the cores are partitioned into multiple voltage and frequency islands (VFIs), and the global interconnect is implemented using a packetswitched network on chip (NoC). In such VFI-based designs, the benefits ...

Institute of Electrical and Electronics Engineers2010

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

Seyed Armin Tajalli, Yusuf Leblebici

A very low power mixed-signal design methodology based on subthreshold source-coupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. T ...

2010

A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

Giovanni Boero, Jens Anders

In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV ...

Springer, 233 Spring Street, New York, Ny 10013, United States2009

Flexible Ultra Low Power Successive Approximation Analog-to-Digital Converter with Asynchronous Clock Generator

Graph Chatbot

Chat with Graph Search

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring

A 16-channel 220 µW neural recording IC with embedded delta compression

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

Clock Distribution Networks in 3-D Integrated Systems

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

A 16-channel 220 µW neural recording IC with embedded delta compression

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

Clock Distribution Networks in 3-D Integrated Systems

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution