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Effects of Process Variations on 3-D Global Clock Distribution Networks

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Skew Variability in 3-D ICs with Multiple Clock Domains

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock di ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Integrated Circuits and Logic Operations Based on Single-Layer MoS2

Andras Kis, Branimir Radisavljevic

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental ...

2011

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010

On the dependability of nanoscale circuits and systems

Milos Stanisavljevic

The invention of the integrated circuit and the manufacturing progress as well as continuing progress in the manufacturing process are the fundamental engines for the implementation of all technologies that support today's information society. The vast maj ...

EPFL2009

Efficiency enhancement and frequency-tunable capability in linear CMOS RF power amplifiers for wireless applications

Paulo Augusto Dal Fabbro

This research work deals with the design of linear CMOS RF power amplifiers. Two important aspects are treated: efficiency enhancement and frequency-tunable capability. For this purpose, two different integrated circuits were realized in a 0.11 µm technolo ...

EPFL2009

Clock and Power Distribution Networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis

Global interconnect design for threedimensional integrated circuits is a crucial task. Despitethe importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal ...

2009

Robust Synchronization of Absolute and Difference Clocks over Networks

Satish Babu Korada

We present a detailed re-examination of the problem of inexpensive yet accurate clock synchronization for networked devices. Based on an empirically validated, parsimonious abstraction of the CPU oscillator as a timing source, accessible via the TSC regist ...

2009

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...

2009

MOS current-mode logic standard cells for high-speed low-noise applications

Stéphane Badel

With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integra ...

EPFL2008

Networks on Chips

Giovanni De Micheli

We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Current integrated circuits contain seve ...

Springer2008