Publication

Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

Related publications (38)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

Graph Chatbot

Chat with Graph Search

Optimization Opportunities in RRAM-based FPGA Architectures

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Storage method and apparatus for random access memory using codeword storage

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

Tunnel Field Effect Transistors

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell