Convex combination initialization method for kohonen neural network implemented in the CMOS technology
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
The paper presents a new initialization mechanism based on a Convex Combination Method (CCM) for Kohonen self-organizing Neural Networks (NNs) realized in the CMOS technology. A proper selection of initial values of the neuron weights exhibits a strong imp ...
Adaptive networks consist of a collection of agents with adaptation and learning abilities. The agents interact with each other on a local level and diffuse information across the network through their collaboration. In this work, we consider two types of ...
Institute of Electrical and Electronics Engineers, Inc., 345 E. 47 th St. NY NY 10017-2394 United States2013
Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to ov ...
Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...
The paper presents how the current leakage encountered in capacitive analog memories affects the learning process of hardware implemented Kohonen neural networks (KNN). MOS transistor leakage currents, which strongly depend on temperature, increase the net ...
This paper presents a complementary metal–oxide– semiconductor (CMOS) implementation of a conscience mechanism used to improve the effectiveness of learning in the winnertakes- all (WTA) artificial neural networks (ANNs) realized at the transistor level. T ...
Institute of Electrical and Electronics Engineers2010
Random telegraph signal (RTS) behavior is reported and characterized in the dark count rate of single-photon avalanche Diodes (SPADs). The RTS is observed in a SPAD fabricated in 0.8-mu m CMOS technology and in four proton-irradiated SPADs designed and fab ...
Institute of Electrical and Electronics Engineers2010
Presented is a transistor-level implementation of a floating and tunable CMOS active inductor. It is based on the classical gyrator-C topology and is enhanced by adding an internal offset reduction mechanism to guarantee functionality also for unbalanced D ...
We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...
Institute of Electrical and Electronics Engineers2011
The paper presents an influence of leakage effect observed in capacitive analog memories on learning process in hardware implemented Kohonen neural networks with MOS transistors used as switches connected with information holding capacitors. The learning r ...
