Publications related to Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...

2017

A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

Mustafa Kilic, Yusuf Leblebici, Themistoklis Mavrogordatos

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The propo ...

2017

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Edoardo Charbon, Harald Arjan Robert Homulle

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmw ...

2016

Non-linear Recovery of Sparse Signal Representations with Applications to Temporal and Spatial Localization

Zafer Dogan

Foundations of signal processing are heavily based on Shannon's sampling theorem for acquisition, representation and reconstruction. This theorem states that signals should not contain frequency components higher than the Nyquist rate, which is half of the ...

EPFL2015

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redund ...

2013

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

Vahid Majidzadeh Bafar

Minimally invasive monitoring of the electrical activity of specific cortical areas using implantable microsystems offers the promise of diagnosing neurological diseases, as well as detecting and identifying neural activity patterns which are specific to a ...

EPFL2012

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

David Atienza Alonso, Pierre Vandergheynst, Nadia Khaled, Hossein Mamaghanian

The long-standing analog-to-digital conversion paradigm based on Shannon/Nyquist sampling has been challenged lately, mostly in situations such as radar and communication signal processing where signal bandwidth is so large that sampling architectures cons ...

2012

Transfer Kinetics of Polar Organic Compounds over Polyethersulfone Membranes in the Passive Samplers Pocis and Chemcatcher

Juliane Hollender

Passive samplers for polar organic compounds often use a polyethersulfone (PES) membrane to retain the particulate sorbent material (e.g., in a POCIS; polar organic chemical integrative sampler) or to reduce the sampling rate and thus extend the kinetic re ...

2012

A 16-channel 220 µW neural recording IC with embedded delta compression

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...

2011

Sampling Trajectories for Mobile Sensing

Martin Vetterli, Jayakrishnan Unnikrishnan

Classical sampling theory for sampling and reconstructing bandlimited fields in

\Re^d

addresses the problem of sampling on lattice points. We consider a generalization of this problem, in which one samples the field along

1

-dimensional spatial trajecto ...

2011

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

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A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Non-linear Recovery of Sparse Signal Representations with Applications to Temporal and Spatial Localization

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing

Transfer Kinetics of Polar Organic Compounds over Polyethersulfone Membranes in the Passive Samplers Pocis and Chemcatcher

A 16-channel 220 µW neural recording IC with embedded delta compression

Sampling Trajectories for Mobile Sensing

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Non-linear Recovery of Sparse Signal Representations with Applications to Temporal and Spatial Localization

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Transfer Kinetics of Polar Organic Compounds over Polyethersulfone Membranes in the Passive Samplers Pocis and Chemcatcher

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

A 16-channel 220 µW neural recording IC with embedded delta compression

Sampling Trajectories for Mobile Sensing

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Design and Exploration of Low-Power Analog to Information Conversion Based on Compressed Sensing