Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor

Silicon nanowire (SiNW) field effect transistors (FETs) have been widely investigated as biological sensors for their remarkable sensitivity due to their large surface to volume ratio (S/V) and high selectivity towards a myriad of analytes through functionalization. In this work, we propose a long channel (L > 500 nm) junctionless nanowire transistor (JNT) SiNW sensor based on a highly doped, ultrathin body field-effect transistor with an organic gate dielectric epsilon(r) = 1.7. The operation regime (threshold voltage V-th) and electrical characteristics of JNTs can be directly tuned by the careful design of the NW/Fin FET. JNTs are investigated through 3D Technology Computer Aided Design (TCAD) simulations performed as a function of geometrical dimensions and channel doping concentration N-d for a p-type tri-gated structure. Two different materials, namely, an oxide and an organic monolayer, with varying dielectric constants er provide surface passivation. Mildly doped N-d = 1 x 10(19) cm(-3), thin bodied structures (fin width F-w < 20 nm) with an organic dielectric (epsilon(r) = 1.7) were found to have promising electrical characteristics for FET sensor structures such as V-th similar to 0 V, high relative sensitivities in the subthreshold regime S > 95%, high transconductance values at threshold g(m),(Vfg=0V) > 10 nS, low subthreshold slopes SS similar to 60 mV/dec, high saturation currents I-d,I-max similar to 1-10 mu A and high I-on/I-off > 10(4)-10(10) ratios. Our results provide useful guidelines for the design of junctionless FET nanowire sensors that can be integrated into miniaturized, low power biosensing systems. (c) 2013 Elsevier B.V. All rights reserved.

FinFET for high sensitivity ion and biological sensing applications

Mihai Adrian Ionescu, Livio Lattanzio, Sara Rigante

A double-gate (DG) fin field effect transistor (FinFET) is discussed as new label-free ion and biological sensor. Simulations as function of channel doping, geometrical dimensions, operation point and materials investigated the device response to an external potential difference which provides a body threshold voltage modulation. The simulation results presented in this work clearly state the key features for an ultrasensitive FET based sensor: an enhancement low doped and partially gated transistor operating in weak-moderate inversion regime. The optimized sensitivity, obtained when the width of the fin is equal to the gate height (W-NW similar to h(g)), reaches a value of 85% for an extraction current, I-d, of 0.1 mu A. These results pave the way for the fabrication process of an innovative CMOS compatible sensing system. (C) 2011 Elsevier B.V. All rights reserved.

2011

Investigation of the dominant 1/f noise source in silicon nanowire sensors

Jan Brunner, Christian David, Sara Rigante

We analyzed 1/f noise in silicon nanowire ion-sensitive field-effect transistors (SiNW-ISFETs) having different wire widths ranging from 100 nm to 1 pin and operated under different gating conditions in order to determine the noise source and the sensor accuracy. We find that the gate-referred voltage noise S-VG (power spectral density) is constant over a large range of SiNWs resistances tuned by a DC gate voltage. The measurements of S-VG for SiNWs with two different gate-oxide thicknesses, but otherwise similar device parameters, are only compatible with the so-called trap state noise model in which the source of 1/f noise is due to trap states residing in the gate oxide (most likely in the interface between the semiconductor and the oxide). S-VG is found to be inversely proportional to the wire width for constant wire length. From the noise data we determine a sensor accuracy of 0.017% of a full Nernstian shift of 60 mV/pH for a SiNW wire with a width of 1 pm. No influence of the ions in the buffer solution was found. (C) 2013 Elsevier B.V. All rights reserved.

Elsevier2014

Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Giovanni De Micheli, Yusuf Leblebici

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their organization onto regular crossbars, the problem of designing the nanowire decoder is still challenging and highly dependent on the nanowire fabrication technology. In this paper, we introduce a novel design style and encoding scheme for decoding nanowires fabricated with the Multi-Spacer-Patterning Technique (MSPT); and we present a method based on Gray codes that reduces the fabrication cost and improves the decoder reliability. We show that by arranging the code in a Gray code fashion, we decrease the fabrication complexity by 17% and the variability by 18% on average. By optimizing the decoder parameters, the simulations showed an improvement of the crossbar yield by 40% and a reduction of the effective bit area by 51% to 169 nm2.

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