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Ultrathin Body InAlN/GaN HEMTs for High-Temperature (600 degrees C) Electronics

Related publications (34)

High-Temperature HEMT Mode

Taking into account the impact of self-heating and temperature rise effects, this work presents a physics-based analytical model for HEMTs, operating continuously from room temperature to high temperatures in linear and saturation regimes. Relying on the c ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Adaptive Body Biasing in Strong Body Factor Technologies

Thomas Christoph Müller

With the advent of intelligent sensor nodes in everyday life, low power aspects of system design become more and more important. Adaptive body biasing is a promising methodology to achieve dynamic adaptation of the tradeoff between performance and energy b ...

EPFL2021

In-depth Cryogenic Characterization of 22 nm FDSOI Technology for Quantum Computation

Edoardo Charbon, Christian Enz, Farzan Jazaeri, Hung-Chi Han, Antonio D'Amico

In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, V back , from 2.95 K back to 300 K. An abrupt drop-of ...

IEEE2021

Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M Beckers

Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative mi ...

EPFL2021

Enhancement Mode Tri-gate GaN Power Devices and Logic Circuits

Minghua Zhu

Gallium Nitride (GaN) is one of the most promising materials for high frequency power switching due to its exceptional properties such as large saturation velocity, high carrier mobility, and high breakdown field strength. The high switching frequency of G ...

EPFL2021

Characterization and Modeling of Mismatch in Cryo-CMOS

Edoardo Charbon, Fabio Sebastiano

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4 ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Mihai Adrian Ionescu, Christian Enz, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

2019

High-Voltage Normally-off Recessed Tri-Gate GaN Power MOSFETs With Low on-Resistance

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Catherine Erine, Minghua Zhu

In this letter, we present normally-off GaN-on-Si MOSFETs based on the combination of tri-gate with a short barrier recess to yield a large positive threshold voltage (VTH) while maintaining a low specific on resistance (R ON,SP ) and high current density ...

2019

High-performance normally-off tri-gate GaN power MOSFETs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Minghua Zhu

In this work, we present the investigation of the combination of gate recess and tri-gate structures to achieve high performance normally-off GaN-on-Si MOSFETs with high positive threshold voltage ( VTH ), low specific on resistance ( RON,SP ) and high out ...

IEEE2019

High-performance nanowire-based E-mode Power GaN MOSHEMTs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Minghua Zhu

In this work, we demonstrate high-performance Enhancement-mode (E-mode) GaN Metal-Oxide-Semiconductor High Electron Mobility Transistors (MOS-HEMTs) on Si substrate achieved by a nanostructured gate region in combination with a large work-function gate met ...

IEEE2019

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