An Interpolated-DFT Synchrophasor Estimation Algorithm and Its Implementation in an FPGA-based PMU Prototype

The accurate measurement of synchrophasors in static and dynamic power network conditions represents one of the main requirements of Phasor Measurement Units (PMUs). International Standards (i.e. the IEEE C37.118) are quickly evolving to drive the technological evolution of these intelligent electronic devices. In this respect, the paper presents an interpolated-DFT based synchrophasor-estimation algorithm that has been designed to meet the accuracy requirements of classes P and M defined in the recent IEEE Std C37.118-2011-1. Together with the analytical description of the main aspects of the proposed synchrophasor estimation algorithm, the paper also presents its implementation inside an FPGA-based PMU prototype. The paper finally shows and discusses some of the compliance tests of the proposed PMU prototype with respect to the above standard.