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Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

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Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

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Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Method for code evaluation using ISI ratio