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3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances area consumption and energy efficiency. Using 10μm-diameter TSV technology, an 8Gb/s serial link consumes only 84fJ/bit with 10X area reduction over 8b parallel bus.
Andreas Peter Burg, Adam Shmuel Teman, Luca Benini, Pascal Andreas Meinerzhagen
Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Kiarash Gharibdoust, Giulia Beanato