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A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

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A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

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The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography