Publications related to A Fast Pruning Technique for Low-Power Inexact Circuit Design

System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

A digital circuit including a signal path with a false path, whereby the signal path includes at least 3 logic instances, the digital circuit further including a logic monitoring element for monitoring a part of the digital circuit, and for outputting a cu ...

2017

Design and Applications of Approximate Circuits by Gate-Level Pruning

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

Energy-efficiency is a critical concern for many systems, ranging from Internet of things objects and mobile devices to high-performance computers. Moreover, after 40 years of prosperity, Moore's law is starting to show its economic and technical limits. N ...

Ieee-Inst Electrical Electronics Engineers Inc2017

A review of sustainable energy access and technologies for healthcare facilities in the Global South

Silvia Hostettler, Andrea Franco, Marjan Shaker, Dikolela Kalubi

Access to reliable, affordable and sustainable energy is essential for improving living standards, development and economic growth. From a healthcare perspective, energy is a critical parameter for delivering and improving healthcare services and life-savi ...

Elsevier Science Bv2017

Global well-posedness for the Yang-Mills equation in 4+1 dimensions: Small energy

Joachim Krieger, Daniel Tataru

We consider the hyperbolic Yang-Mills equation on the Minkowski space

\reels^{4+1}

. Our main result asserts that this problem is globally well-posed for all initial data whose energy is sufficiently small. This solves a longstanding open problem. ...

Annal Mathematics2017

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Yusuf Leblebici

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations an ...

Elsevier Science Bv2017

Towards Near-Threshold Server Processors

David Atienza Alonso, Babak Falsafi, Marina Zapater Sancho, Luca Benini, Ali Pahlevan, Pablo Garcia del Valle, Javier Picorel Obando, Arash Pourhabibi Zarandi

The popularity of cloud computing has led to a dramatic increase in the number of data centers in the world. The ever-increasing computational demands along with the slowdown in technology scaling has ushered an era of power-limited servers. Techniques suc ...

IEEE/ACM2016

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

A Sub-mW Pulse-Based 5-bit Flash ADC with a Time-Domain Fully-Digital Reference Ladder

Alexandre Schmid, Yusuf Leblebici, Nikola Katic, Radisav Cojbasic

Journal article A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder: A Katic, Nikola; Cojbasic, Radisav; Schmid, Alexandre; Leblebici, Yusuf Published in: Microelectronics Journal (ISSN: 0026-2692), vol. 46, num. 12, ...

Elsevier2015

Polarity Control at Runtime

Michele De Marchi

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to ov ...

EPFL2015

Automatic Generation of Inexact Digital Circuits by Gate-level Pruning

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

Inexact or approximate circuits show great ability to reduce power consumption at the cost of occasional errors in comparison to their conventional counterparts. Even though the benefits of such circuits have been proven for many applications, they are not ...

2015

A Fast Pruning Technique for Low-Power Inexact Circuit Design

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System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths

Design and Applications of Approximate Circuits by Gate-Level Pruning

A review of sustainable energy access and technologies for healthcare facilities in the Global South

Global well-posedness for the Yang-Mills equation in 4+1 dimensions: Small energy

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Towards Near-Threshold Server Processors

New Data Structures and Algorithms for Logic Synthesis and Verification

A Sub-mW Pulse-Based 5-bit Flash ADC with a Time-Domain Fully-Digital Reference Ladder

Polarity Control at Runtime

Automatic Generation of Inexact Digital Circuits by Gate-level Pruning

Global well-posedness for the Yang-Mills equation in 4+1 dimensions: Small energy

Automatic Generation of Inexact Digital Circuits by Gate-level Pruning

Polarity Control at Runtime

New Data Structures and Algorithms for Logic Synthesis and Verification

Towards Near-Threshold Server Processors

A Sub-mW Pulse-Based 5-bit Flash ADC with a Time-Domain Fully-Digital Reference Ladder

System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths

A review of sustainable energy access and technologies for healthcare facilities in the Global South

Design and Applications of Approximate Circuits by Gate-Level Pruning

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies