Optimization Strategy of Numerical Simulations Applied to EPFL Substrate Model

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci
Ieee, 2014
Conference paper

Abstract

A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing on the accuracy of the EPFL Substrate Model when compared to finite element simulations. A two-dimensional case study on a parasitic lateral bipolar is then proposed with both spice-like and finite element simulation results for the minority carriers diffusion. A linear model is developed to estimate the most important geometrical domains influencing the accuracy of the studied model.

Official source

https://infoscience.epfl.ch/record/205626?ln=en

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Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift diffusion. In this case the conductivity of the substrate is spatially modulated and this effect is particularly important in high injection regime. In this work a description of the coupling between majority and minority drift diffusion currents is presented. A distributed model of the substrate is then proposed to take into account the conductivity modulation and its feedback on diffusion processes. The model is expressed in terms of equivalent circuits in order to be fully compatible with circuit simulators. The simulation results are then discussed for diodes and bipolar transistors and compared to the ones obtained from physical device simulations and measurements. (C) 2014 Published by Elsevier Ltd.

Elsevier2015

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

Ieee-Inst Electrical Electronics Engineers Inc2016

Modeling of optoelectronic devices involves long and complex numerical simulations, usually performed with TCAD tools. Numerical simulations provide accurate results for a single device but are not feasible when dealing with a full circuit comprising several nodes. To solve this issue, we developed a novel approach to simulate optoelectronic devices in standard SPICE circuit simulators, thus avoiding using TCAD tools. The concept is based on a coarse meshing of the semiconductor whose nodes are interconnected with the so-called Generalized Lumped Devices. The Generalized Lumped Devices are four ports devices: two ports simulate real currents and voltages in the semiconductor while two additional ports simulate excess carrier density and gradient through the definition of equivalent currents and voltages. The model behind the Generalized Devices is physics based and can correctly simulate optical generation of excess carriers, drift-diffusion transport, bulk and surface recombination as well as capacitive effects, without the need to introduce fitting or empirical parameters. Moreover, since all inputs and outputs are electrical quantities, the model is fully SPICE-compatible and can be merged with SPICE netlists of circuits. In this work, we use the Generalized Devices approach to simulate a bipolar phototransistor and prove that we can predict the photocurrent versus the collector voltage, for different illumination intensities. The model accurately takes into account the optically-triggered current amplification in the phototransistor. Sentaurus TCAD numerical simulations are in agreement with the Generalized Devices approach. Finally, since the model is physics based, we could assess the impact of different semiconductor parameters, such as doping concentrations, lifetime, surface recombination velocity, on the output characteristics of the phototransistors, directly with SPICE circuit simulators.

SPIE-INT SOC OPTICAL ENGINEERING2020