Publications related to Multiple-Independent-Gate Nanowire Transistors: From Technology to Advanced SoC Design

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Clarissa Convertino

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power ...

NATURE RESEARCH2021

On the Dynamic Performance of Laterally Gated Transistors

Elison de Nazareth Matioli, Armin Jafari, Catherine Erine, Giovanni Santoruvo

Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter c ...

2019

CJM: A Compact Model for Double-Gate Junction FETs

Jean-Michel Sallese, Farzan Jazaeri, Matthias Bucher

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-n ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi, Maxime Victor Thammasack, Tsung-Han Lin, David Baudouin

The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this br ...

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A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

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We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

2017

Single field effect transistor capacitor-less memory device and method of operating the same

Mihai Adrian Ionescu, Arnab Biswas, Nilay Dagtekin

A single field effect transistor capacitor-less memory device, and method of operating the same, including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transisto ...

Technology Transfer Office EPFL2016

Performance of arsenene and antimonene double-gate MOSFETs from first principles

Nicola Marzari, Giovanni Pizzi, Marco Gibertini

In the race towards high-performance ultra-scaled devices, two-dimensional materials offer an alternative paradigm thanks to their atomic thickness suppressing short-channel effects. It is thus urgent to study the most promising candidates in realistic con ...

Nature Publishing Group2016

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Giovanni De Micheli, Shashi Kanth Bobba

As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits, thereby opening up venues for new transistor channel materials based on nanowires and nanotubes. Transistors based on nanowires and nanotubes inhe ...

Ieee-Inst Electrical Electronics Engineers Inc2015

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Multiple-Independent-Gate Nanowire Transistors: From Technology to Advanced SoC Design

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Exploration of Negative Capacitance Devices and Technologies

On the Dynamic Performance of Laterally Gated Transistors

CJM: A Compact Model for Double-Gate Junction FETs

Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Single field effect transistor capacitor-less memory device and method of operating the same

Performance of arsenene and antimonene double-gate MOSFETs from first principles

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Graph Chatbot

Chat with Graph Search

On the Dynamic Performance of Laterally Gated Transistors

Performance of arsenene and antimonene double-gate MOSFETs from first principles

Exploration of Negative Capacitance Devices and Technologies

Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach

Single field effect transistor capacitor-less memory device and method of operating the same

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

CJM: A Compact Model for Double-Gate Junction FETs