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Multi-Gigabyte On-Chip DRAM Caches for Servers

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Multi-Gigabyte On-Chip DRAM Caches for Servers

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Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

Performance Contracts for Software Network Functions

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Prefetched Address Translation

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses