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A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

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A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

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The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Methods and systems for power-efficient inductive chip-to-chip communications

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

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