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In this article, a cryo-CMOS receiver integrated with a frequency synthesizer for scalable multiplexed readout of qubits is presented, focusing on radio frequency (RF) reflectometry readout of silicon-based semiconductor spin qubits/quantum dots. The propo ...
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing an ...
The aim of this thesis is to implement, analyze and improve the selected low noise clock
generation and distribution techniques for ADC implementations. The thesis is divided into
two parts. The first part focuses on the sampling phase generation and distr ...
An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Desi ...
In this paper we investigate the direct effect of resonator quality factor (Q) on the oscillator phase noise. We use 2-port contour mode resonators (CMRs), fabricated both with aluminum nitride (AlN) and aluminum scandium nitride (AlScN), as the frequency- ...
This paper describes a balanced frequency shift keying (FSK) modulation, namely quasi-balanced FSK (QB-FSK), for energy-efficient high-data-rate communication. Not suffering from data-pattern dependency, the proposed modulation method enables frequency mod ...
Nowadays, the internet of things (IoT) nodes have started to spread in various domains of our society, from the industrial to the domestic environment. The remote sensing is one among their fundamental functions. The implementation of a radio detection and ...
This paper presents the design of a 60GHz Quadrature Digitally-Controlled Oscillator for a low-power Frequency-Modulated Continuous Wave radar System-on-Chip. The accurate detection of vital signs requires 1 and Q demodulation of the received signal. The q ...
This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of -258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves -65 dBc ...
