Low Noise Clock Generation: Modeling, Analysis and Implementation

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distribution from a low noise clock source. The development and the implementation of the low noise sampling clock phase generation system for a 16-channel TI-SAR ADC while taking advantage of 28nm FDSOI technology is presented. A delay-locked-loop (DLL) is used for this purpose with a 750MHz input frequency. To change the delay, the body-bias technique of the FDSOI technology is utilized so that the number of noise contributors within the delay line is reduced. To use body- biases of both the PMOS and NMOS transistors, a dual-control mechanism which consists of coarse and fine controls has been developed. Moreover, to increase the range of the delay generated by the delay line, a range extender circuit which drives only one charge pump input is developed. This also reduces the charge pump noise added to the system. There are two tape-outs done for the DLL. The first tape-out includes only a delay line and compares simulation results with the measurement for the delay generated. The results show that the simulations and the measurements are consistent. The second tape-out includes the DLL with the 16-channel TI-SAR ADC. The DLL measurements show that the delay range is almost doubled and around ±11%. However, the noise generated within the loop can not be observed with the measurement setup, and it is believed that it is buried under the noise coming from other sources. Secondly, The detailed analysis and the modeling of sub-sampling phase-locked-loop (SSPLL) is done. The aim is to find the limits of its capture range, and to improve the stability margins. The stability limits are also established mathematically. The SSPLL modeling is done in discrete time domain, which allows fast simulations in MATLAB. The capture range is analyzed for different aspects and simulated in MATLAB. Firstly, the linear range extension of the phase detector is examined for both the first and the second order loops. It is shown that the first order loop extends the capture range as the linear range is extended due to the reduction in the phase detector gain. Secondly, sub-sampling phase detector (SSPD) with master-slave switch implementation is examined in discrete time domain for timing nonidealities. The MATLAB simulations also show that the phase margin decreases significantly with large capture ranges, and it is shown that adding a secondary path which delays the sampled voltage one clock cycle increases the phase margin. The last part of the thesis focuses on the circuit implementation of SSPLL with increased phase margin in 28nm FDSOI technology. The aim is to understand how much the lock range is affected when implemented with the transistor level circuit elements. Moreover, the major nonlinearity sources of the SSPLL are investigated. It is observed that the main nonlinearity source is the VCO. It is seen that the capture ranges of both SSPD versions are around ±0.3 of the reference frequency, which is close to the one given by the MATLAB simulations.