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Ambipolar silicon nanowire field effect transistor

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Transient Off-Current in Junctionless FETs

Jean-Michel Sallese, Didier Bouvet, Farzan Jazaeri, Lucian Barbut

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Ieee-Inst Electrical Electronics Engineers Inc2013

ZrO2/InAlN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with InAlN Barrier of Different Compositions

Nicolas Grandjean, Jean-François Carlin

We report on InAlN/GaN heterostructure metal-oxide-semiconductor field-effect transistors (MOSHFETs) with an InAlN barrier layer of different compositions (x(InN) 13, 17, and 21%) and ZrO2 gate-insulator/passivation. Static measurements yielded higher drai ...

Iop Publishing Ltd2013

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Physical Synthesis onto Sea-of-Tiles with Double-Gate Silicon Nanowire Transistors

Giovanni De Micheli, Yusuf Leblebici, Shashi Kanth Bobba, Michele De Marchi

We have designed and fabricated double-gate ambipolar field-effect transistors, which exhibit p-type and n-type characteristics by controlling the polarity of the second gate. In this work, we present an approach for designing an efficient regular layout, ...

Ieee2012

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We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Elsevier2012

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

Institute of Electrical and Electronics Engineers2012

Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effec ...

Institute of Electrical and Electronics Engineers2012

Impact Ionization and Carrier Multiplication in Graphene

Yusuf Leblebici, Luca Pirro

We develop a model for carrier generation by impact ionization in graphene, which shows that this effect is non-negligible because of the vanishing energy gap, even for carrier transport in moderate electric fields. Our theory is applied to graphene field ...

American Institute of Physics2012

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high- ...

EPFL2011