900 V Reverse-Blocking GaN-on-Si MOSHEMTs With a Hybrid Tri-Anode Schottky Drain
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Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...
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we report a new single photon avalanche diode (SPAD) implemented in a commercially available high-voltage CMOS technology. The SPAD was designed with relatively low-doped layers to form p-/n- junction, instead of commonly adopted p+/n- or n+/p- structures. ...
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Series connected (stacked) CMOS vertical Hall devices were analyzed on the basis of performance of a single five contacts device biased at different common mode voltages with respect to the substrate. The uneven influence of junction field effect on residu ...
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This work reports on memory applications of punch-through impact ionization single-transistor latch (PIMOS), showing abrupt current switching (3-10mV/dec.) as well as hysteresis in both ID(VDS) and ID(VGS). A capacitor-less 1PIMOS - 1 MOSFET DRAM memory is ...
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