Publications related to Clock Jitter Compensation in High-Rate ADC Circuits

Unlabeled Sensing of Multi-Input FRI Signals

Shannon's sampling theorem for bandlimited signals, formulated in 1949, has become a cornerstone for modern digital communications and signal processing. The importance of sampling and reconstruction of analog signals has led to great advances in the field ...

2022

Uncertain Sampling with Certain Priors

Golnooshsadat Elhami

Sampling has always been at the heart of signal processing providing a bridge between the analogue world and discrete representations of it, as our ability to process data in continuous space is quite limited. Furthermore, sampling plays a key part in unde ...

EPFL2021

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi, Ahmad Fallahpour, Amirhossein Mohajerin Ariaei, Cong Liu

Sinc-shaped temporal pulse trains have a spectrally efficient, rectangular Nyquist spectrum. We demonstrate the simultaneous and reconfigurable optical generation of multiple Nyquist-shaped wavelength-division-multiplexed (WDM) channels having temporal sin ...

OPTICAL SOC AMER2019

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Mustafa Kilic, Yusuf Leblebici

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additi ...

IEEE2018

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Mustafa Kilic, Yusuf Leblebici

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...

2017

How does one compute the noise power to simulate real and complex GNSS signals?

Cyril Botteron, Jérôme Leclère

Simulation of GNSS signals is very important to test and validate algorithms. With some algorithms, such as acquisition or tracking, we do not need to simulate a realistic constellation with actual ranges, Doppler or navigation data. We can simply simulate ...

2016

Sampling and Reconstruction of Shapes with Algebraic Boundaries

Martin Vetterli, Arash Amini, Mitra Fatemi

We present a sampling theory for a class of binary images with finite rate of innovation (FRI). Every image in our model is the restriction of

\mathds{1}_{\{p\leq0\}}

to the image plane, where

\mathds{1}

denotes the indicator function and

p

is some r ...

2016

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Edoardo Charbon, Harald Arjan Robert Homulle

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmw ...

2016

Clock Jitter Compensation in High-Rate ADC Circuits

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Unlabeled Sensing of Multi-Input FRI Signals

Uncertain Sampling with Certain Priors

High-Speed ADC Design and Optimization for Wireline Links

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

How does one compute the noise power to simulate real and complex GNSS signals?

Sampling and Reconstruction of Shapes with Algebraic Boundaries

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Unlabeled Sensing of Multi-Input FRI Signals

Uncertain Sampling with Certain Priors

Sampling and Reconstruction of Shapes with Algebraic Boundaries

High-Speed ADC Design and Optimization for Wireline Links

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

How does one compute the noise power to simulate real and complex GNSS signals?

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC