Publications associées à Clock Jitter Compensation in High-Rate ADC Circuits

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Sampling and Reconstruction of Shapes with Algebraic Boundaries

Martin Vetterli, Arash Amini, Mitra Fatemi

We present a sampling theory for a class of binary images with finite rate of innovation (FRI). Every image in our model is the restriction of

\mathds{1}_{\{p\leq0\}}

to the image plane, where

\mathds{1}

denotes the indicator function and

p

is some r ...

2016

Clock Jitter Compensation in High-Rate ADC Circuits

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Unlabeled Sensing of Multi-Input FRI Signals

Uncertain Sampling with Certain Priors

High-Speed ADC Design and Optimization for Wireline Links

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

How does one compute the noise power to simulate real and complex GNSS signals?

Sampling and Reconstruction of Shapes with Algebraic Boundaries

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Unlabeled Sensing of Multi-Input FRI Signals

Uncertain Sampling with Certain Priors

Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

How does one compute the noise power to simulate real and complex GNSS signals?

High-Speed ADC Design and Optimization for Wireline Links

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Sampling and Reconstruction of Shapes with Algebraic Boundaries