Publication

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Related publications (123)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Graph Chatbot

Chat with Graph Search

Another transistor-based revolution: on-chip qPCR

All-optical polariton transistor

A Common Core Model for Junctionless Nanowires and Symmetric Double Gate FETs

Beyond Scaling

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Tunable floating active inductor with internal offset reduction

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Ferroelectric Field Effect Transistor for Memory and Switch Applications