Publication

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Related publications (103)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Graph Chatbot

Chat with Graph Search

Highly Parallel RTL Simulation

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

FPGA Architecture: Principles and Progression

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

LUT-Based Optimization For ASIC Design Flow

Design and experimental validation of an FPGA-based PMU simultaneously compliant with P and M performance classes