Publications related to Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Analysis and Optimization of MPSoC Reliability

Giovanni De Micheli, Yusuf Leblebici, Ayse Kivilcim Coskun

Advancements in technology enable integration of multiple devices on a single core, resulting in increased on chip power and temperature densities. Higher temperatures, in turn, present a significant challenge for reliability. In this work we propose a com ...

2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

2006

Networks on Chips: Technology and Tools

Giovanni De Micheli, Luca Benini

The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communica ...

Morgan Kaufmann2006

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006

Mapping and Configuration Methods for Multi-Use-Case Networks on Chips

Giovanni De Micheli, Srinivasan Murali

To provide a scalable communication infrastructure for Systems on Chips (SoCs), Networks on Chips (NoCs), a communication centric design paradigm is needed. To be cost effective, SoCs are often programmable and integrate several different applications or u ...

2006

A Low-Power Adaptive Bias/Clock Generator for Fine-Grained Voltage and Frequency Scaling in Multi-Core Systems

Yusuf Leblebici, Zeynep Toprak Deniz

This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...

2005

NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

Giovanni De Micheli, David Atienza Alonso, Nicolas Genko

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular ...

2005

Fabrication and electrical characterization of high performance copper/polyimide inductors

Mihai Adrian Ionescu, Catherine Dehollain, Didier Bouvet, Cyrille Hibert

This paper presents fabrication and RF characterization results of spiral inductors fabricated using a developed damascene-like thick-copper / polyimide process module. This module has low thermal budget and is compatible with current IC interconnect archi ...

2005

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Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Analysis and Optimization of MPSoC Reliability

Log-based architectures for general-purpose monitoring of deployed code

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Networks on Chips: Technology and Tools

Routing Aware Switch Hardware Customization for Networks on Chips

Mapping and Configuration Methods for Multi-Use-Case Networks on Chips

A Low-Power Adaptive Bias/Clock Generator for Fine-Grained Voltage and Frequency Scaling in Multi-Core Systems

Optimization of Reliability and Power Consumption in Systems on a Chip

NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

Fabrication and electrical characterization of high performance copper/polyimide inductors

Graph Chatbot

Chat with Graph Search

Analysis and Optimization of MPSoC Reliability

Networks on Chips: Technology and Tools

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Mapping and Configuration Methods for Multi-Use-Case Networks on Chips

A Low-Power Adaptive Bias/Clock Generator for Fine-Grained Voltage and Frequency Scaling in Multi-Core Systems

Routing Aware Switch Hardware Customization for Networks on Chips

Fabrication and electrical characterization of high performance copper/polyimide inductors

Log-based architectures for general-purpose monitoring of deployed code

Optimization of Reliability and Power Consumption in Systems on a Chip

NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration