Resource Trade-Offs in Circuits and Systems: from Neurotechnology to Communications

This thesis aims to explore and exploit trade-offs in integrated circuits and systems to overcome the fundamental bottlenecks faced by future data acquisition and communication systems. Specifically, we target the emerging implantable neurotechnology and the advancing highspeed communication domains as case studies. The first part of the thesis addresses the extreme resource constraints of implantable neurotechnology. As the number of electrodes for neural recording reaches towards thousands, a single-chip solution is rendered infeasible in terms of both energy and area. To tackle this problem, we present an analog front-end architecture that applies various energy- and areasaving techniques to reduce the hardware resource demand of neural recording. The second challenge has been transferring the massive data throughput over a wireless link to allow neural recording in independent environments. Inspired by the previous ideas for compression and the emerging machine learning applications in neuroscience, we introduce an on-chip adaptive feature extraction framework to reduce the overall data rate to the feasible range. The second part of the thesis focuses on the timing uncertainty problem in high-speed communication systems. The increasing data rates in wireline and wireless transceivers, and the emerging need for multitransceiver architectures necessitate the lowest energy and area for the frequency synthesis, which contradicts the current jitter-cost trade-off paradigm. To allow the use of area-efficient ring oscillators for jitter-sensitive applications under low-power constraints, we introduce a multiphase feedback phase-locked loop architecture, which suppresses the oscillator phase noise over a larger bandwidth.

Low Complexity Scheduling and Coding for Wireless Networks

Siddhartha Brahma

The advent of wireless communication technologies has created a paradigm shift in the accessibility of communication. With it has come an increased demand for throughput, a trend that is likely to increase further in the future. A key aspect of these challenges is to develop low complexity algorithms and architectures that can take advantage of the nature of the wireless medium like broadcasting and physical layer cooperation. In this thesis, we consider several problems in the domain of low complexity coding, relaying and scheduling for wireless networks. We formulate the Pliable Index Coding problem that models a server trying to send one or more new messages over a noiseless broadcast channel to a set of clients that already have a subset of messages as side information. We show through theoretical bounds and algorithms, that it is possible to design short length codes, poly-logarithmic in the number of clients, to solve this problem. The length of the codes are exponentially better than those possible in a traditional index coding setup. Next, we consider several aspects of low complexity relaying in half-duplex diamond networks. In such networks, the source transmits information to the destination through

n

half-duplex intermediate relays arranged in a single layer. The half-duplex nature of the relays implies that they can either be in a listening or transmitting state at any point of time. To achieve high rates, there is an additional complexity of optimizing the schedule (i.e. the relative time fractions) of the relaying states, which can be

2^n

in number. Using approximate capacity expressions derived from the quantize-map-forward scheme for physical layer cooperation, we show that for networks with

n\leq 6

relays, the optimal schedule has atmost

n+1

active states. This is an exponential improvement over the possible

2^n

active states in a schedule. We also show that it is possible to achieve at least half the capacity of such networks (approximately) by employing simple routing strategies that use only two relays and two scheduling states. These results imply that the complexity of relaying in half-duplex diamond networks can be significantly reduced by using fewer scheduling states or fewer relays without adversely affecting throughput. Both these results assume centralized processing of the channel state information of all the relays. We take the first steps in analyzing the performance of relaying schemes where each relay switches between listening and transmitting states randomly and optimizes their relative fractions using only local channel state information. We show that even with such simple scheduling, we can achieve a significant fraction of the capacity of the network. Next, we look at the dual problem of selecting the subset of relays of a given size that has the highest capacity for a general layered full-duplex relay network. We formulate this as an optimization problem and derive efficient approximation algorithms to solve them. We end the thesis with the design and implementation of a practical relaying scheme called QUILT. In it the relay opportunistically decodes or quantizes its received signal and transmits the resulting sequence in cooperation with the source. To keep the complexity of the system low, we use LDPC codes at the source, interleaving at the relays and belief propagation decoding at the destination. We evaluate our system through testbed experiments over WiFi.

EPFL2015

Multi-unit global energy management and optimization for network-on-chip applications

Zeynep Toprak Deniz

The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The significance of the problem is underlined by the increasing prominence of multi-core systems that must operate under strict power/energy budget constraints, both in mobile applications and in cases where special cooling arrangements can be very expensive. A range of solutions have been proposed over the last few years, which are mostly based on static, off-line calculation of a limited set of operating points in the form of optimum voltage and frequency assignments, that are subsequently chosen according to actual demands. Still, to our best knowledge, none of these studies have demonstrated an on-line solution to complex, multi-variable energy optimization problem which allows dynamic adjustment of individual operating frequencies and supply voltages of multiple processing elements. This thesis presents the design and silicon implementation of an analog-based energy optimizer unit, which is capable of dynamically adjusting power supply and clock frequencies of multiple embedded cores, tailored to the instantaneous workload information (computational task) and fully adaptive to variations in process and temperature. Our approach borrows from the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple processing elements, converging on the global minima of the constrained optimization problem which are represented as stable operating points of a simple feedback loop. It is already well known that stable, approximate solutions of multi-variable optimization problems (such as gradient descent) can be obtained by using very compact analog circuits, e.g. resistive networks. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoff's current law constraints in an equivalent resistive network is exploited. The implementation of the on-line analog optimizer is then discussed. The realization of the blocks composing the system architecture is described, and circuit design issues are studied thoroughly. The three-loop demonstrator circuit of the proposed analog optimizer architecture has been implemented using a 0.18μm standard digital CMOS process. The overall circuit area of the optimizer is (245μm × 650μm) excluding decoupling capacitors, while each loop circuit occupies only (180μm × 120μm). Operating at a nominal supply of 1.8 V, the circuit is capable of supporting the desired frequency range of 170 MHz - 290 MHz, as well as the voltage range of 1.2 V - 1.8 V. Estimated workload levels for each task (loop) are provided as 4-bit binary inputs, and the corresponding solution for minimum energy consumption is observed as assigned supply voltages and operating frequencies for each processing element, for a certain task duration. The measured worst-case settling time for supply voltages is less than 50μs. The average power consumption of the entire three-loop optimizer is 4mW. Measurements experimentally validate the concept of fully analog, current-based solution to implement on-line energy minimization in complex multi-core systems under varying workload conditions. Key functional blocks of the proposed circuit operate in weak inversion, resulting in very low power dissipation for the optimizer. The prototype successfully demonstrates that the proposed optimizer block is also capable of taking into account the on-chip variations of temperature as well as process parameters. As such, it can be used as a generic building block for on-line energy optimization in complex systems.

EPFL2006

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

David Atienza Alonso, Pascal Frossard, Karim Kanoun

We consider the problem of energy-efficient on-line scheduling for slice-parallel video decoders on multicore systems. We assume that each of the processors are Dynamic Voltage Frequency Scaling (DVFS) enabled such that they can independently trade off performance for power, while taking the video decoding workload into account. In the past, scheduling and DVFS policies in multi-core systems have been formulated heuristically due to the inherent complexity of the on-line multicore scheduling problem. The key contribution of this report is that we rigorously formulate the problem as a Markov decision process (MDP), which simultaneously takes into account the on-line scheduling and per-core DVFS capabilities; the power consumption of the processor cores and caches; and the loss tolerant and dynamic nature of the video decoder’s traffic. In particular, we model the video traffic using a Direct Acyclic Graph (DAG) to capture the precedence constraints among frames in a Group of Pictures (GOP) structure, while also accounting for the fact that frames have different display/decoding deadlines and non-deterministic decoding complexities. The objective of the MDP is to minimize long-term power consumption subject to a minimum Quality of Service (QoS) constraint related to the decoder’s throughput. Although MDPs notoriously suffer from the curse of dimensionality, we show that, with appropriate simplifications and approximations, the complexity of the MDP can be mitigated. We implement a slice-parallel version of H.264 on a multiprocessor ARM (MPARM) virtual platform simulator, which provides cycle-accurate and bus signal-accurate simulation for different processors. We use this platform to generate realistic video decoding traces with which we evaluate the proposed on-line scheduling algorithm in Matlab.

Ieee-Inst Electrical Electronics Engineers Inc2013