High voltage power supply system for tethered drone part II

A high voltage power supply system for a tethered drone is presented. The project is a follow-up to a previous semester project and the purpose of this project is to review the implementation, improve the design and solve problems. The system consists of an inverter part, a transformer part and a rectifier part. The input voltage is 600 VDC and the output voltage is 12VDC for a maximum power of 1500W. The inverter part is composed of 4 transistors controlled by two gate drivers. On the other side of the transformer, we have a bridge rectifier which will be implemented in 3 different ways: a full-bridge diode and two new active rectification systems, including mosfets and controllers. We will first present the different systems chosen, review the previous part and make improvements, then we will implement these new systems, design the prototypes and make tests for each system. Finally, we will test the whole converter.

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

In the last decade the power consumption of electronic devices has increased for both static and active components. Following the Dennard's scaling rule, as long as the transistor sizes are reduced then the supply voltage (VDD) can also be scaled in order to increase the area density and maintain or improve the performances. However, scaling VDD and thus shifting the threshold voltage (Vth) of 60mV in a metal-oxide semiconductor field-effect transistor (MOSFET) increases the OFF state current (Ioff ) by a factor of 10 in the ideal case. The reason for this is that the inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of 60mV/decade. To overcome this limit, novel device concepts have been proposed and the tunnel field-effect transistor (TFET) is one of the most promising because it resembles a MOSFET and should enable to achieve sub-60mV/dec SS, low Ioff and small VDD. The aim of this thesis is to investigate the potential of TFETs by the fabrication and characterization of InAs/Si as p-channel and InAs/GaSb as n-channel device for a complementary TFET technology. III-V nanowires are grown via metal-organic chemical vapor deposition (MOCVD) and are integrated on Si(100) substrates using a novel technique called template-assisted selective epitaxy (TASE), which enables the fabrication of vertical and lateral III-V hetero-structure TFETs. Sub-40nm nanowire cross-section InAs/Si p-TFETs and InAs/GaSb n-TFETs in-plane on Si are demonstrated for the first time. The InAs/Si p-TFETs exhibit state-of-the art performances with an ON state current (Ion) of 4uA/um at VGS=VDS=-0.5V, ON/OFF ratio of 1x10E5 with SSavg of 70-80mV/dec at room temperature. The InAs/GaSb n-TFETs have an order of magnitude larger Ion but the SS is limited by the non-optimized gate-stack on InAs channel and by the depletion of the undoped GaSb source. Different operation regimes of TFETs are investigated by temperature-dependent measurements,Wentzel-Kramers-Brillouin (WKB) modeling and TCAD simulations, indicating that the switching region for InAs/Si is dominated by the presence of traps at the hetero-junction. The abruptness of the band-edges in InAs/GaSb is studied by the extraction of the conductance slope in fabricated p-n and p-i-n tunnel diodes.

EPFL2016

An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier

Yimai Peng

Piezoelectric energy harvesters (PEHs) are widely deployed in many self-sustaining systems, and proper rectifier circuits can significantly improve the energy conversion efficiency and, thus, increase the harvested energy. Various active rectifiers have been proposed in the past decade, such as synchronized switch harvesting on inductor (SSHI) and synchronous electric charge extraction (SECE). This article presents a sense-andset (SaS) rectifier that achieves maximum-power-point-tracking (MPPT) of PEHs and maintains optimal energy extraction for different input excitation levels and output voltages. The proposed circuit is fabricated in the 0.18-μm CMOS process with a 0.47-mm 2 core area, a 230-nW active power, and a 7-nW leakage power. Measured with a commercial PEH device (Mide PPA-1022) at 85and 60-Hz vibration frequency, the proposed circuit shows 512% and 541% power extraction improvement [figure of merit (FoM)] compared with an ideal full-bridge rectifier (FBR) for ON-resonance and OFF-resonance vibrations, respectively, while maintaining high efficiency across different input levels and PEH parameters.

IEEE2019

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

EPFL2016