27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC
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The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...
Shannon's sampling theorem for bandlimited signals, formulated in 1949, has become a cornerstone for modern digital communications and signal processing. The importance of sampling and reconstruction of analog signals has led to great advances in the field ...
The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...
The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...
Calibration of time-interleaved analog-to-digital converters is a problem whose necessity and complexity increase with the number of interleaved channels. In this study, we develop a generic representation of the referenceless timing mismatch calibration s ...
In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...
A 0.88 mm 2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 p ...
A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) opera ...
Calibration of time-interleaved analog-to-digital converters is a problem whose necessity and complexity increase with the number of interleaved channels. In this study, we develop a generic representation of the referenceless timing mismatch calibration s ...
This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-dig ...