Publication
System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms
Related publications (33)
METROII: A Design Environment for Cyber-Physical Systems
Cyber-Physical Systems are integrations of computation and physical processes and as such, will be increasingly relevant to industry and people. The complexity of designing CPS resides in their heterogeneity. Heterogeneity manifest itself in modelin ...
2013A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS
Yusuf Leblebici, Lukas Kull, Thomas Toifl
An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC sta ...
2013Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache
Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories — block-based and page-based. The former organize data in conventional blocks (e.g., 64B), ensurin ...
ACM2013High-temperature compatible 3D-integration processes for a vacuum-sealed CNT-based NEMS
Nico de Rooij, Danick Briand, Terunobu Akiyama, Rokhaya Gueye
A System-in-Package (SiP) concept for the 3D-integration of a Single Wall Carbon Nanotube (SWCNT) resonator with its CMOS driving electronics is presented. The key element of this advanced SiP is the monolithic 3D-integration of the MEMS with the CMOS elec ...
SPIE - International Society of Optical Engineering2013Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
Michail Zervas, Yusuf Leblebici, Alessandro Cevrero, Yüksel Temiz, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini
An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...
2012Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors
Edoardo Charbon, Ties Jan Henderikus Kluter, Claudio Favi, Christian Mester
We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...
2012A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory
Giovanni De Micheli, Luca Benini
The performance of most digital systems today is limited by the interconnect latency between logic and memory, rather than by the performance of logic or memory itself. Three- dimensional (3-D) integration using through-silicon-vias (TSVs) may provide a so ...
2012Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
Luca Benini, Federico Angiolini, Subhasish Mitra
Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the f ...
2011Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology
We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...
Institute of Electrical and Electronics Engineers2011Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu
Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores tha ...
Springer New York2011