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A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

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A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

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Chat with Graph Search

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs

Multi-Gigabyte On-Chip DRAM Caches for Servers

ShiDianNao: shifting vision processing closer to the sensor

Approximate Computing With Unreliable Dynamic Memories

Accurate Power Analysis for Near-Vt RRAM-based FPGA

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

BuMP: Bulk Memory Access Prediction and Streaming

Single event upset mitigation in low power SRAM design

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache