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Energy-Efficient Electronic Functions Based on the Co-integration of 2D and Ferroelectric Materials

Related publications (144)

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Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Mihai Adrian Ionescu, Jean-Michel Sallese, Farzan Jazaeri, Amin Rassekh

In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness ...

2020

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabr ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Synaptic transistors with aluminum oxide dielectrics enabling full audio frequency range signal processing

Danick Briand, Alessio Mancinelli

The rapid evolution of the neuromorphic computing stimulates the search for novel brain-inspired electronic devices. Synaptic transistors are three-terminal devices that can mimic the chemical synapses while consuming low power, whereby an insulating diele ...

2020

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâs la ...

EPFL2019

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

Sub-Thermionic Scalable III-V Tunnel Field-Effect Transistors Integrated on Si (100)

Mihai Adrian Ionescu, Kirsten Emilie Moselund

We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p(+) GaAsSb raised source epitaxial re ...

IEEE2019

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Ion sensitive field effect transistors (ISFETs) form a very attractive solution for wearable sensors due to their capacity for ultra-miniaturization, low power operation, and very high sensitivity, supported by complementary metal oxide semiconductor (CMOS ...

2019

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Christian Enz, Farzan Jazaeri, Arnout Lodewijk M Beckers

This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of tempe ...

2019

Multi-Objective System-Level Management of Modern Green Data Centers

Ali Pahlevan

In our modern society, the average citizen has turned into a daily cloud user. Despite being virtually transparent for the user, internet services require data centers behind the scenes. Data centers burn several megawatts of power and their electricity bi ...

EPFL2019