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In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...
In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The propo ...
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and theref ...
We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmw ...
Sampling moiré effects are well known in signal processing. They occur when a continuous periodic signal g(x) is sampled using a sampling frequency fs that does not respect the Nyquist condition, and the signal frequency f folds-over and gives a new, false ...
A CMOS image sensor including at least one pixel and one circuit arranged to receive, on a first node of the circuit, an analog signal representative of the luminosity level received by the pixel, the circuit being capable of successively acquiring 2n samp ...
Sampling moiré effects occur due to aliasing (foldover) when a continuous periodic signal g(x) is sampled using a sampling frequency that does not respect the Nyquist condition. However, visible beating artifacts may also occur when g(x) is sampled using s ...
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of c ...
This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this ...
The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are t ...
