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A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

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A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

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Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Synthesis of Dual Mode Logic

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Method for speeding up boolean satisfiability

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Synthesis of Dual Mode Logic

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

Method for speeding up boolean satisfiability