Discrete Time Analysis of Phase Detector Timing Nonidealities in Type-I Sub-Sampling PLL

The analysis of the effect of sub-sampling phase detector (SSPD) timing nonidealities on Type-I sub-sampling phase-locked loop (SSPLL) is presented. The nonidealities considered are the delay between the complementary sampling clocks and the propagation delays due to the switch on-resistances. The complementary-clocked switches are implemented as the phase detector. The analysis is done in discrete time domain to include the sampling effect. The difference equations are constructed to determine the stability bounds. The simulations are done in MATLAB by iterating the equations. It is shown that the delay between the complementary sampling clocks results in two stability bounds compared to the one bound in the ideal case, and the on-resistance of the second switch also creates a similar effect. The on-resistance of the first switch does not degrade the stability range, but it may reduce the lock range. Moreover, the effect of nonlinearity on the loop is demonstrated with an example on the loop lock behavior with different initial conditions.