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Forward Error Correction for Multipath Media Streaming

Related publications (28)

Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Chuan Zhang

Since polar were ratified as part of the 5G standard, low-complexity polar decoders with close-to-optimum error-rate performance have received significant attention. Compared to successive cancellation (SC) decoding, both SC list and SC flip decoding can i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren, Chuan Zhang

Compared with the bit-wise successive cancellation list (SCL) decoding of polar codes, the node-based Fast SCL decoding significantly reduces the decoding latency by identifying special constituent codes and decoding these in parallel. To further reduce th ...

IEEE2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets

Orion Afisiadis, Mathieu Pierre Xhonneux

LoRaWAN is nowadays one of the most popular protocols for low-power Internet of Things communications. Although its physical layer, namely LoRa, has been thoroughly studied in the literature, aspects related to the synchronization of LoRa receivers have re ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

List Ordered Statistics Decoders for Polar Codes

Andreas Peter Burg, Yifei Shen, Chuan Zhang

The de-facto standard decoding algorithm for polar codes, successive cancellation list (SCL) decoding, is a breadth-first search algorithm. By keeping a list of candidate codewords, SCL decoding improves the performance as the list size L increases. Howeve ...

IEEE2022

Flow Time Scheduling and Prefix Beck-Fiala

Ola Nils Anders Svensson, Lars Rohwedder

We relate discrepancy theory with the classic scheduling problems of minimizing max flow time and total flow time on unrelated machines. Specifically, we give a general reduction that allows us to transfer discrepancy bounds in the prefix Beck-Fiala (bound ...

ASSOC COMPUTING MACHINERY2022

Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits

Giovanni De Micheli, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Buffer and splitter (B/S) cells must be inserted to an AQFP circuit to meet the technology-imposed constraints on path balancing and fanout branching. These cells a ...

ACM2022

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Hassan Harb

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, th ...

SPRINGER2022