Concept

Circuit intégré à signaux mixtes

Publications associées (586)

Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herei ...

2016

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Denis Sallin

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses ...

EPFL2016

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

Maria-Anna Chalkiadaki

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless bo ...

EPFL2016

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results

Stanisa Raspopovic, Roberto Puddu

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCM ...

Springer Verlag2016

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack, Marios Barlas

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Plasmonic nanohole arrays on Si-Ge heterostructures: An approach for integrated biosensors

Hatice Altug, Liza Carol Andrea Dunbar, Dordaneh Etezadi, Cenk Ibrahim Özdemir

Nanohole array surface plasmon resonance (SPR) sensors offer a promising platform for high-throughput label-free biosensing. Integrating nanohole arrays with group-IV semiconductor photodetectors could enable low-cost and disposable biosensors compatible t ...

Spie-Int Soc Optical Engineering2016

Substrate Current Optimization in Smart Power ICs

Pietro Buccella

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits ...

EPFL2016

Active Guard Ring Characterization for Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper shows SPICE simulation results of active guard ring structures which are typically employed in Smart Power ICs. Active guard rings act as barriers limiting the flow of minority carriers injected into the substrate toward sensitive circuits. The ...

Ieee2016

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

Alexios Konstantinos Balatsoukas Stimming

The goal of channel coding is to detect and correct errors that appear during the transmission of information. In the past few decades, channel coding has become an integral part of most communications standards as it improves the energy-efficiency of tran ...

EPFL2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementar ...

Ieee-Inst Electrical Electronics Engineers Inc2016

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