Concept

Procédé planar

Publications associées (42)

In-plane fabrication of insulated gold-tip probes for electrochemical and force spectroscopy molecular experiments

Nico de Rooij, Terunobu Akiyama, Sebastian Gautsch, Peter Van der Wal, Yexian Wu

A new and versatile fabrication process of insulated gold tip probes for atomic force microscopy (AFM) is presented by Wu et al. (In-plane fabricated insulated gold-tip probe for electrochemical and molecular experiments, in: 2013 IEEE 26th International C ...

Elsevier2014

Reusable plasmonic substrates fabricated by interference lithography: a platform for systematic sensing studies

Olivier Martin, Thomas Gerd Siegfried

Surface-enhanced Raman scattering (SERS) has become increasingly popular in the scientific and industrial communities because of its analytical capabilities and potential to study fundamentals in plasmonics. Although under certain conditions extremely high ...

Wiley-Blackwell2013

Miniature curved artificial compound eyes

Dario Floreano, Ramon Pericet Camara, Michal Karol Dobrzynski, Géraud L'Eplattenier

In most animal species, vision is mediated by compound eyes, which offer lower resolution than vertebrate single-lens eyes, but significantly larger fields of view with negligible distortion and spherical aberration, and high temporal resolution in a tiny ...

National Academy of Sciences2013

Inkjet-printed SU-8 Hemispherical Microcapsules and Silicon chip Embedding

Jürgen Brugger, Massimo Mastrangeli, Victor Javier Cadarso Busto, Rosario Maurizio Gullo, Loïc Jacot-Descombes

Planar lithography techniques are not effective for precise fabrication of microdevices with hemispherical shapes. Drop-on-demand (DOD) inkjet printing (IJP) of photo-curable ink is a more appropriate fabrication approach as it takes advantage of the surfa ...

2013

All-stencil transistor fabrication on 3D silicon substrates

Jürgen Brugger, Luis Guillermo Villanueva Torrijo, Andreea Veronica Savu, Cyrille Hibert, Cristina Martin Olmos, Philippe Langlet, Oscar Vazquez Mena, Peter Vettiger, Katrin Sidler Arnet

The standard lithographic techniques to fabricate electronic components involve the use of polymers, baking steps and chemicals. This typically restricts their application to flat substrates made up of standard materials. Stencil lithography has been propo ...

Iop Publishing Ltd2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Surface Microstructures on Planar Substrates and Textile Fibers Guide Neurite Outgrowth: A Scaffold Solution to Push Limits of Critical Nerve Defect Regeneration?

Thomas Lehnert, Li Yao

The treatment of critical size peripheral nerve defects represents one of the most serious problems in neurosurgery. If the gap size exceeds a certain limit, healing can't be achieved. Connection mismatching may further reduce the clinical success. The pre ...

Public Library Science2012

Three-Dimensional Writing of Highly Stretchable Organic Nanowires

Giorgio Margaritondo

Three-dimensional (3D) writing is a promising approach to realize stretchable electronics, but is so far limited to microscale features. We developed accurate 3D writing for highly stretchable organic nanowire arrays using a nanoscale polymer meniscus. Spe ...

2012

Development and characterization of EIS structures based on SiO2 micropillars and pores before and after their functionalization with phosphonate films

Anna Fontcuberta i Morral, Anna Dalmau Mallorquí

In this work electrolyte insulator semiconductor (EIS) structures based on lithographically fabricated Si SiO2 micropillars and pores are studied. The samples are characterized by means of impedance spectroscopy (IS) and they are compared to samples with a ...

2011

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011

Graph Chatbot

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Connectez-vous pour utiliser Chat avec Graph Search