PCI Express

Résumé

Le PCI Express (Peripheral Component Interconnect Express), officiellement abrégé PCI-E ou PCIe est un standard de bus d'extension utilisé pour les échanges entre les cartes d'extension (cartes graphiques, SSD, disques durs, cartes réseau,…) et avec la carte mère d'un ordinateur. Développé par Intel et introduit en 2004, il supplante les standards antérieurs PCI, PCI-X et AGP. Par analogie avec le modèle OSI, le standard PCI Express spécifie une couche physique, dont un bus local, couramment appelé (« bus PCI express »), une couche liaison de données et une couche de transaction. Le PCI-SIG (Special Interest Group) est le groupe de travail, représentant plus de huit cent sociétés, qui s'occupe du maintien et du développement du standard PCI Express. La dernière version du standard est la spécification PCI Express 6.0, offrant un débit de par canal, publiée le 11 janvier 2022. La version 7.0 du protocole est à l'étude. PCI Express est une marque déposée. Une évolution du P

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https://fr.wikipedia.org/wiki/PCI_Express

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A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Andrei Ardelean, Claudio Bruschini, Edoardo Charbon, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gates, guaranteed by the circuit architecture to be nonoverlapping and covering the totality of the sensor's exposure period. The gates can be adjusted with a temporal resolution of 17.9 ps, and the minimum measured gate width is 0.99 ns; to our knowledge, the shortest reported to date among large-format SPAD imagers. In the dual-channel mode, the burst frame rate is 49.8 and 97.7 kframes/s in the single-channel mode. A 2690-MB/s PCI express (PCIe) interface has been added to the data acquisition framework, enabling continuous operation at approximately 44 and 88 kframes/s. Due to optimizations of the gate-signal tree, we achieved a significant reduction to gate skew and gate width variation, which is negligible with respect to the SPAD temporal jitter. These improvements, along with sub-10-cps dark count rate (DCR) per pixel and 50% maximum photon detection probability (PDP), result in a sensor particularly well suited for fast acquisition fluorescence lifetime imaging microscopy (FLIM) experiments, for which we demonstrate reduced dispersion versus a single-gated sensor.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

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Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries due to their massively data-parallel nature and high memory bandwidth. Recent work on designing join algorithms for CPUs has shown that carefully tuned join implementations that exploit underlying hardware can outperform naive, hardware-oblivious counterparts and provide excellent performance on modern multicore servers. However, there has been no such systematic analysis of hardware-conscious join algorithms for GPUs that systematically explores the dimensions of partitioning (partitioned versus non-partitioned joins), data location (data fitting and not fitting in GPU device memory), and access pattern (skewed versus uniform). In this paper, we present the design and implementation of a family of novel, partitioning-based GPU-join algorithms that are tuned to exploit various GPU hardware characteristics for working around the two main limitations of GPUs–limited memory capacity and slow PCIe interface. Using a thorough evaluation, we show that: i) hardware-consciousness plays a key role in GPU joins similar to CPU joins and our join algorithms can process 1 Billion tuples/second even if no data is GPU resident, ii) radix partitioning-based GPU joins that are tuned to exploit GPU hardware can substantially outperform non-partitioned hash joins, iii) hardware-conscious GPU joins can effectively overcome GPU limitations and match, or even outperform, state-of-the-art CPU joins.

IEEE2019

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A phase-contrast-imaging core fluctuation diagnostic and first-principles turbulence modeling for JT-60SA

Stephan Brunner, Stefano Coda, Aylwin Iantchenko, Kenji Tanaka, Matthieu Toussaint

A core fluctuation diagnostic based on the phase-contrast imaging (PCI) technique has been designed for the JT-60SA tokamak, with the assistance of a synthetic diagnostic coupled to a gyrokinetic code. Using a tangentially viewing geometry, this system would be able to resolve small-scale microturbulence as well as macroscopic fluctuations, with good spatial and temporal resolution, throughout the plasma cross-section and in all plasma regimes. The spatial resolution will be optimal (

2021

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